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<div class="header">
  <div class="headertitle"><div class="title">TIM_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>TIM.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
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Public Attributes</h2></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>TIM. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a7a81e7aac9bef80b126097f8e9f36d07" name="a7a81e7aac9bef80b126097f8e9f36d07"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7a81e7aac9bef80b126097f8e9f36d07">&#9670;&#160;</a></span>AF1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TIM_TypeDef::AF1</td>
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<p>TIM alternate function option register 1, Address offset: 0x60 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1e2d623b6e3ef17672550a56cb01354f">&#9670;&#160;</a></span>AF2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TIM_TypeDef::AF2</td>
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<p>TIM alternate function option register 2, Address offset: 0x64 </p>

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<a id="a6a42766a6ca3c7fe10a810ebd6b9d627" name="a6a42766a6ca3c7fe10a810ebd6b9d627"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6a42766a6ca3c7fe10a810ebd6b9d627">&#9670;&#160;</a></span>ARR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TIM_TypeDef::ARR</td>
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<p>TIM auto-reload register, Address offset: 0x2C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a137d3523b60951eca1e4130257b2b23d">&#9670;&#160;</a></span>BDTR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TIM_TypeDef::BDTR</td>
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<p>TIM break and dead-time register, Address offset: 0x44 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad7271cc1eec9ef16e4ee5401626c0b3b">&#9670;&#160;</a></span>CCER</h2>

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<p>TIM capture/compare enable register, Address offset: 0x20 </p>

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<p>TIM capture/compare mode register 1, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa8129ca70a2232c91c8cfcaf375249f6">&#9670;&#160;</a></span>CCMR2</h2>

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<p>TIM capture/compare mode register 2, Address offset: 0x1C </p>

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<p>TIM capture/compare mode register 3, Address offset: 0x54 </p>

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<p>TIM capture/compare register 1, Address offset: 0x34 </p>

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<p>TIM capture/compare register 2, Address offset: 0x38 </p>

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<p>TIM capture/compare register 3, Address offset: 0x3C </p>

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<p>TIM capture/compare register 4, Address offset: 0x40 </p>

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<p>TIM capture/compare register5, Address offset: 0x58 </p>

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<p>TIM capture/compare register6, Address offset: 0x5C </p>

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<p>TIM counter register, Address offset: 0x24 </p>

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<p>TIM control register 1, Address offset: 0x00 </p>

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<p>TIM control register 2, Address offset: 0x04 </p>

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<p>TIM DMA control register, Address offset: 0x48 </p>

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<p>TIM DMA/interrupt enable register, Address offset: 0x0C </p>

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<p>TIM DMA address for full transfer, Address offset: 0x4C </p>

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<p>TIM event generation register, Address offset: 0x14 </p>

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<p>TIM prescaler, Address offset: 0x28 </p>

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<p>TIM repetition counter register, Address offset: 0x30 </p>

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<p>Reserved, 0x50 </p>

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<p>TIM slave mode control register, Address offset: 0x08 </p>

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<p>TIM status register, Address offset: 0x10 </p>

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<p>TIM Input Selection register, Address offset: 0x68 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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